Through-wafer interconnection is a structure that electrically connects devices (e.g. integrate circuits and microelectronic devices such as sensors, imagers and transducers) on the front side to the backside of the wafer. Unlike a conventional bond pad interconnection structure that requires out-of-wafer wiring to connect the devices on the front side to the backside, through-wafer interconnection makes the electric connection using a conductor that runs directly through the wafer.
Through-wafer interconnection is highly desired for the high density array of the devices to save the space on the wafer surface. There is a great need for miniaturization of electronic components such as ICs, microelectronic devices used in sensor arrays, transducer arrays, and photo imager arrays, and modules that are used in portable devices like cellular phones and PDAs. Miniaturization not only results in a reduced foot print of the components on the printed board, it can also have a positive effect on the device performance. The ultimate miniaturization is reached when the component is packaged into a chip size package. Conventional methods to enable chip size packaging include routing the bonding pads of ICs into, for example a ball grid array configuration. For some devices, such as those that have vertical discrete components and stacked planar dies, rerouting alone is not sufficient. A different method is needed to enable addressing the backside such that these devices can be packaged into CSP. In this regard, through-wafer interconnection has been proven to be a powerful technique. In addition, through-wafer interconnection allows wafer-level processing that results in simultaneous fabrication of large number of packages. This advantage limits the additional packaging cost that might have incurred due to the high complexity of the technology. It also avoids of the long wires running in or across the wafer surface and thus reduces the undesired parasitic capacitance and high interconnection resistance.
Most through-wafer connections are done with through-wafer vias or holes, which are filled with a connective material. A prior art through-wafer interconnect is shown in FIG. 1. The through-wafer interconnect is built in a via through a substrate 10 by first making a hole 12, then forming a seed layer 14 on surfaces of the hole 12 and subsequently forming a metal layer 16 (e.g., using electroplating methods) on the seed layer 14. The metal layer 16 serves as a through-wafer conductor to electrically connect devices or connectors (not shown) on one side of the substrate 10 to devices or connectors on the other side. In a typical application, devices are on the top side of the substrate 10. The through-wafer conductor (metal layer 16) connects the devices to a connector (such as a connection pad or connection ball) on the backside.
The fabrication process of the above-shown through-wafer interconnections is usually complex and requires rather sophisticated technologies. The fabrication process also lacks freedom for design optimizations. For example, the thickness of the metal layer 16 as shown in FIG. 1 is inherently limited by the existing electroplating techniques. The resultant through-wafer interconnects also lacks physical flexibility. It is therefore desirable to introduce new designs of through-wafer interconnection to improve the fabrication process and the performance of through-wafer interconnects.